VLIW SYSTEM WITH PREDICATED INSTRUCTION EXECUTION FOR INDIVIDUAL INSTRUCTION FIELDS

In the case of constituting a processing unit having the characteristic of a VLIW type processing unit and the characteristic of a pipeline type processing unit, since reference to the result of operations is made among a plurality of processing units executing in parallel the operations, transfer of the register file is frequently generated among the processing units, resulting in insufficient effect of the high speed operations. In view of solving this problem, the predicate registers are provided and moreover a means for broadcasting the update data of the predicate register to all processing units is also provided. Thereby, operations for obtaining branching condition and numerical value can be realized in different processing units and the number of steps of the processing program can be reduced. In addition, since high speed transfer between the processing units of the data register having a wider bit width is no longer required and thereby the mounting area can be reduced and high speed processing unit can be realized.