AUTOMATED VALIDATION AND VERIFICATION OF COMPUTER SOFTWARE

A method and apparatus for automating validation and verification of computer software that confirms during a test execution of the software that all lines of code are executed and all branches in the software are taken or not taken at least once. The computer software to be tested is compiled and a link map is generated. After compilation of the code, it is run in a test fixture to test all the required functions. During this test execution, a monitoring process is performed which documents which lines of code have been executed and whether certain branches of the code were either taken or not taken. An execution record is generated which indicates what instruction branches were taken and were not taken. A comparison is then made between the link map originally generated and the instruction record generated to determine what lines of code were executed, whether each branch was taken at least once, and whether a branch was not taken at least once.