A METHOD FOR DETECTING UPDATES TO INSTRUCTIOND WHICH ARE WITHIN AN INSTUCTION PROCESSING PIPELINE OF A MICROPROCESSOR

A core snoop buffer apparatus is provide which stores addresses of pages from which instructions have been fetched but not yet retired (i.e. the instructions are outstanding within the instruction processing pipeline). Addresses corresponding to memory locations being modified are compared to the addresses stored in the core snoop buffer on a page basis. If a match is detected, then instructions are flushed from the instruction processing pipeline and refetched. In this manner, the instructions executed to the point of modifying registers or memory are correct in self-modifying code or multiprocessor environments. Instructions may be speculatively fetched and executed while retaining coherency with respect to changes to memory. The number of pages from which instructions are concurrently outstanding within the microprocessor are typically small compared to the number of cache lines outstanding or the number of instructions outstanding. Therefore, a relatively small hardware structure may be employed to perform the instruction coherency functionality.