INTEGRATED STRUCTURE LAYOUT AND LAYOUT OF INTERCONNECTIONS FOR AN INTEGRATED CIRCUIT CHIP

An integrated structure layout of functional blocks and interconnections for an integrated execution unit of an integrated circuit chip. The functional blocks of the integrated execution unit include data dependency comparator logic, tag assignment logic, and register file port multiplexer logic. The data dependency logic receives address signals for a group of instructions and passes dependency information output to the tag assignment logic. The tag assignment logic provides tag information output to the register file port multiplexer logic. The tag assignment logic is arranged on opposite sides of a center channel, so that the tag information output is laid-out in the center channel and is fed directly to the register file port multiplexer logic in a substantially straight path. The register file port multiplexer logic directs the tag information output to a register file address port of a register file.