SEMICONDUCTOR WAFER PROCESSING SYSTEM

A semiconductor wafer processing system having a multi-layered arrangement of wafer processing units included in a spinner to carry out photoresist coating and developing processes for the formation of micro patterns on semiconductor wafers, thereby enabling an easy increase in those processing units coping with an introduction of new processes without increasing the occupying space of the processing units, while being capable of achieving accurate wafer feeding and loading operations, and minimizing the consumption of a chemical solvent coated over wafers. The system includes groups of modules each being selected from first and second modules. The first module includes a plurality of bake units each having bake boxes arranged in a multi-layered fashion, the bake units being arranged adjacent to one another in the wafer feeding direction, and a spin unit, such as a spine coater or a spine developer, fixedly mounted on the bake units. The second module includes a plurality of wafer edge exposure units arranged in a multi-layered fashion while being arranged in such a fashion that they are adjacent to one another in the wafer feeding direction, and a spin unit fixedly mounted on the wafer edge exposure units. Each module group constitute a station, together with a feeding robot. A feeing interface or buffer stocker is arranged between adjacent stations.