SEMICONDUCTOR INTEGRATED CIRCUIT UTILIZING INSULTED GATE TYPE TRANSISTORS

For raising the accuracy of analog multiplication, a gate-drain (G-D) connection point of transistor (Tr) whose gate-drain (G-D) are shorted and whose source is connected to ground potential is connected to a source of second Tr whose G-D are shorted, a first input signal current source is connected to a G-D connection point of the second Tr, a G-D connection point of third Tr whose G-D are shorted and whose source is connected to the ground potential is connected to a source of fourth Tr whose G-D are shorted, a second input signal current source is connected to a G-D connection point of the fourth Tr, the G-D connection points of the second and fourth Tr's are connected to first and second capacitors respectively, outputs of the first and second capacitors are connected to each other and to a gate of fifth Tr to form a floating point, a source of the fifth Tr is connected to the ground potential, and a drain current of the fifth Tr is an operation output.