Patent US 6,133,762

This invention involves logic circuits formed of metal oxide semiconductor field effect transistors having differing threshold voltages. In a first embodiment, the logic circuit includes a first and a second series connection. The first series connection between a first supply voltage and an output node consists of a source-drain path of an N-channel transistor having a high threshold voltage and a pull-down conditional conduction path of a pull-down network constructed exclusively of transistors having a low threshold voltage. The second series connection between said supply voltage and said output node consists of a source-drain path of a P-channel transistor having the high threshold voltage and a pull-up conditional conduction path of a pull-up network constructed exclusively of transistors having the low threshold voltage. The two high threshold voltage MOSFETs receive at their respective gates inverse signals so that either both are conducting or both are off. The pull-down network and pull-up network each receives input signals which control whether they conduct. These input signals are preferably selected so that the pull-down network and pull-up network do not conduct simultaneously. The two parts of each series connection may be in either order. The first input signal is preferably a clock signal. The pull-down network is preferably constructed exclusively of N-channel transistors. The pull-up network is preferably constructed exclusively of P-channel transistors.