INTERFACING DEVICE TO EXTRACT M SETS OF BITS OUT OF N SETS OF BITS, CONTROL UNIT AND LOGICAL CELL

An interfacing device (INT) which extracts M outgoing sets of bits (OS1, OS2, . . . , OSM) out of N incoming sets of bits (IS1, IS2, . . . , ISN), M being smaller than N, includes: PA1 a. an incoming register (IR) wherein the N incoming sets of bits (IS1, IS2, . . . , ISN) are temporarily stored; and PA1 b. a selector (SEL) comprising a multiplexer bank (MUX) with M multiplexers (MUX1, MUX2, . . . , MUXM) each having N-M+1 inputs and one output, and a control unit (CTRL) for the multiplexer bank (MUX). The distinct sets of N-M+1 incoming sets of bits that are applied to distinct multiplexers overlap and the control unit (CTRL) can control the multiplexers (MUX1, MUX2, . . . , MUXM) so that an appropriate order is respected by the outgoing sets of bits (OS1, OS2, . . . , OSM).