Patent №
US 6,175,950
Granted
2001-01-16
Filed 1998
Owner
LSI LOGIC CORPORATION
+1 more
Lab
—
AI components
1
planning
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
09062217
Net routing is optimized in an integrated circuit device by dividing an integrated circuit design with a first group of substantially parallel lines in a first direction and with a group of substantially parallel lines in a second direction, with the second direction being substantially perpendicular to the first direction. A first routing graph is formed with vertices corresponding to locations where lines in the first direction and lines in the second direction cross, and nets are globally routed as a function of the first routing graph. The integrated circuit design is further subdivided with a second group of substantially parallel lines in the first direction, and a second routing graph is formed with vertices corresponding to locations where lines in the first and second groups of substantially parallel lines in the first direction cross lines in the group of substantially parallel lines in the second direction. For a net globally routed using the first routing graph, a first local net is formed in a first fragment of the second routing graph, and the first local net is rerouted within the first fragment by computing edge penalty values for edges in the first fragment and rerouting the first local net as a function of the edge penalty values.
AI classification
Ownership
LSI LOGIC CORPORATION
assignment · 91240764
LSI LOGIC CORPORATION, A DELAWARE CORPORATION
assignment · 94390085
Assignors
ANDREEV, ALEXANDER, SCEPANOVIC, RANKO, RASPOPOVIC, PEDJA
On an employer assignment, the assignors are typically the inventors.