METHOD AND SYSTEM FOR DESIGN VERIFICATION

The present invention pertains to a dynamic process for generating biased pseudo-random test patterns for the functional verification of a microprocessor having a bus interface unit that is capable of direct memory access (DMA) operations between I/O devices attached to an external bus and the microprocessor's memory. The test patterns verify memory operations performed by the microprocessor and DMA operations received by the microprocessor's bus interface unit. These test patterns can then be used by a simulation mechanism to simulate the expected results of the target microprocessor running the generated sequence of transactions. The test verification system categorizes the verifiable operations into transactions. Each transaction is assigned a user-defined weight that is used to bias the frequency that a transaction is tested. The test verification system selects a particular transaction category based on the user-defined weights and generates the corresponding instructions or test patterns that implement the transaction.