DUAL VT SRAM CELL WITH BITLINE LEAKAGE CONTROL

In some embodiments, the invention includes an integrated circuit including a bitline and a bitline#, wordlines, and memory cells. The memory cells each corresponding to one of the wordlines and each include first and second pass transistors coupled between first and second storage nodes, respectively, and the bitline and bitline#, respectively, the corresponding wordline being coupled to gates of the first and second pass transistors. The memory cells include first and second inverters cross-coupled between the first and second storage nodes, wherein the first and second pass transistors each have a lower threshold voltage than do transistors of the first and second inverters. Wordline voltage control circuitry coupled to the wordlines selectively controls wordline signals on the wordlines. In some embodiments, the wordline voltage control circuitry asserts the wordline signal for a selected wordline corresponding to a memory cell selected to be read and underdrives the wordline signals for the wordlines not corresponding to the selected memory cell.