GRID LAYOUTS OF SWITCHING AND SORTING NETWORKS

A systematic method for creating layouts for various sorting and switching networks on VLSI chips is proposed. These sorting and switching networks include butterfly switching networks, benes networks, odd-even sorting networks, and bitonic sorting networks. The present invention utilizes the existing VLSI grid-model to create various layouts. A rectangular layout is proposed which introduces the use of an additional row to create an area-efficient layout for various switching networks. A diamond layout is proposed which further improves rectangular layout by reducing the number of columns required. A suitable combination of diamond and rectangular layouts is also proposed.