MICROPROCESSOR

A microprocessor is disclosed, which determines hit/miss by comparing four tag RAMs 5.times.4 times to improve economical efficiency of a device. The microprocessor includes a first latch for reserving a virtual address whose low bits are identical with a physical address and high bits are different from the physical address; a TLB including TLB indexes having bits smaller than the high bits, for determining hit/miss of the virtual address by receiving the high bits of the virtual address from the first latch; a TLB miss handler for mutually inputting/outputting data with the TLB to produce and store new data in the TLB; a multiplexer for receiving the output of the TLB or the TLB miss handler; a plurality of tag RAMs including CAM cells which stores tag RAM indexes to be compared with the TLB indexes, for selecting the tag RAM indexes corresponding to the low 12 bits of the virtual address; a first comparator for comparing the selected tag RAM indexes with the TLB indexes; a cache miss handler for storing new data in the tag RAMs by receiving the outputs of the multiplexer and the first comparator; data RAMs having the same number of the tag RAMs, for outputting data corresponding to the tag RAM indexes which are identical with the TLB indexes; and a data latch for storing the outputs of the data RAMs and outputting them outside.