METHOD TO REDUCE WIRE-OR GLITCH IN HIGH PERFORMANCE BUS DESIGN TO IMPROVE BUS PERFORMANCE
Patent №
US 6,310,489
Granted
2001-10-30
Filed 1996
Owner
SUN MICROSYSTEMS, INC.
Lab
—
AI components
1
hardware
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
08640096
A system and method of reducing wire-or glitch to improve bus speeds. In a system that supports wire-or functions, the rise time of the wave created by the off-going driver is controlled. The off-going wave is forced to climb gradually such that one propagation delay of the loaded bus later, it is only marginally above a high threshold voltage. The fall time of the wave created by an on-going driver is minimized such that a strong negative going voltage propagates down the bus. This strong negative going voltage drags a composite wave on the bus (i.e. the combination of the waves of the on-going driver and the off-going driver) back below a low threshold voltage approximately one propagation delay after the switching occurs.
AI classification
Ownership
SUN MICROSYSTEMS, INC.
assignment · 80960911
Assignors
YUAN, LEO, CHENG, CHRISTOPHER
On an employer assignment, the assignors are typically the inventors.