D-TYPE MASTER-SLAVE FLIP-FLOP

A D-type master-slave flip-flop includes a master unit receiving an input variable and producing two first intermediate variables, a transfer unit including at least two logic gates and a clock connection connected to one input of each of the gates, which are adapted to supply two second intermediate variables as a function of the input variable and the clock signal and are looped to the master unit, and a slave unit to form at least one output variable. Another input of a first gate of the transfer unit is connected to the master unit to receive directly the true value of one of the variables supplied by the master unit. Another input of the second gate of the transfer unit is connected to the master unit to receive therefrom the complement of the same variable. The second intermediate variables are independent of each other. The flip-flop has the advantage that it is insensitive to the slopes of the flanks of the clock signals.