TEST RESULTS CHECKING VIA PREDICTIVE-REACTIVE EMULATION

A function for verifying the behavior of a digital system, where the digital system can exhibit several differing but valid behaviors from the same input. Identical input vectors are applied to both a hardware model and hardware emulator of the digital system via a simulator. Simulating the hardware emulator generates one or more predicted output vectors, while simulating the hardware model produces a single output vector. The output vector of the hardware model is then compared with the one or more predicted output vectors of the hardware emulator. If there is not an output match, an exception is raised. If the output vector of the hardware model matches one of the predicted output vectors of the hardware emulator, a rules checker applies a set of context specific rules defining a valid behavior to the current matching output vector, the internal model state information from the hardware emulator, and a history file of previous output vectors. If the current matching output vector passes the rules checker, the hardware emulator reacts by updating its internal state information and the verification continues with a new input vector, otherwise an exception is raised indicating a rules violation.