PROCESSOR EMULATION INSTRUCTION COUNTER VIRTUAL MEMORY ADDRESS TRANSLATION

When emulating a Target architecture on a Host system having a different architecture, virtual-to-real address translation is typically expensive in terms of computer cycles. The cost for translating addresses for instruction fetches can be significantly reduced by maintaining both a virtual and a real memory address instruction counter. Both are incremented on each instruction fetch. Virtual to real address translation is eliminated as long as execution continues on the same real memory page of instructions. Alternatively, only a real memory address instruction counter is incremented, while maintaining a delta instruction counter value to efficiently translate back and forth to and from the corresponding virtual memory address.