Flash based control for field programmable gate array

A circuit for controlling a switching transistor in a reprogrammable FPGA device comprises first and second floating gate flash memory transistors. A first floating gate flash memory transistor has a drain electrically coupled to a first voltage potential, a floating gate, a control gate coupled to a control gate node, and a source coupled to an output node. A second floating gate flash memory transistor has a drain electrically coupled to the output node, a floating gate, a control gate coupled to the control gate node, and a source coupled to a second voltage potential. The output node is coupled to the gate of a switching transistor.