ACCESSING BYTE LINES FORM DUAL MEMORY BLOCKS AND ALIGNING FOR VARIABLE LENGTH INSTRUCTION EXECUTION

A data access circuit for a CPU that individually extracts and processes variable length data or commands from a memory in one clock period provides high speed processing. The circuit includes a program counter for increasing a previous address by a currently decoded command length to compute the next address. The program counter outputs the next address to a data storing unit and a data alignment unit. The data storing unit can include two memories with two decoders and outputs a prescribed length of data corresponding to the next address from the program counter. The data alignment unit aligns the prescribed amount of data output from the data storing unit using the next address. A command decoding unit decodes the aligned data in order to determine a next command and its variable command length, which is used to reset the currently extracted command length used by the program counter. A command execution unit executes the next command received from the command decoding unit.