SYSTEM AND METHOD FOR CACHE PROCESS

Patent №

US 6,385,697

Granted

2002-05-07

Filed 1999

Owner

NEC CORPORATION

Lab

AI components

1

hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

09461092

In a cache system, a non-FSA (Full-Set Associative) cash table such as a DM (Direct Mapping) cache table is coupled with an FSA cache table. Tag comparison for cache hit judgment is executed simultaneously in the two cache tables. The number of cache hits to each cache line of the FSA cache table is counted by an access counter, and an access count value concerning the cache hit count is stored in an access count area of each cache line. When a cache hit occurred to a cache line of the FSA cache table, the access count value of the cache line is incremented by 1. When a miss hit occurred to both cache tables, the access count values of all the cache lines of the FSA cache table are decremented by 1 at once. If miss hits occurred to both cache tables when the DM cache table has an invalid cache line corresponding to the index of input address data, data fetched from main memory due to the miss hits is written into the invalid cache line corresponding to the index. If the miss hits occurred when the DM cache table has no invalid cache line corresponding to the index and the FSA cache table is full of valid cache lines, data stored in the miss hit cache line of the DM cache table is transferred to one of cache lines of the FSA cache table having the smallest access count value, and data fetched from the main memory is written into the miss hit cache line of the DM cache table. By such data management/transfer, the cache hit rate and data access speed are increased to higher levels.

AI hardwareG06F 12/122G06F 12/0897

AI classification

AI hardware0.72
Machine learning0.01
Natural language0.00
Evolutionary computation0.00
Vision0.00
Speech0.00
Knowledge representation0.00
Planning0.00

Ownership

NEC CORPORATION

assignment · 104500345

Assignors

MIYAZAKI, MITSUHIRO

On an employer assignment, the assignors are typically the inventors.

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