TERNARY CAM CELL WITH DRAM MASK CIRCUIT

A ternary CAM cell including a binary SRAM CAM cell connected in series with a mask transistor between a match line and a discharge line, and a DRAM mask circuit for applying a mask (care/don't care) value to the gate terminal of the mask transistor. The binary CAM cell stores a data value that is compared with an applied data value, and opens the first portion of a discharge path between the match line and the discharge line when the applied data value fails to match the stored data value. The mask transistor is controlled by the DRAM mask circuit, which includes two associated DRAM memory cells that are connected by a bit line to a sense amplifier. The DRAM mask circuit is refreshed such that, during a read phase of the refresh operation, a data value is read only from the first DRAM memory cell and registered (refreshed) by the sense amplifier circuit. In the subsequent write phase of the refresh operation, the data value is written to the second DRAM memory cell. The storage node of the second DRAM memory cell is connected to the gate terminal of the mask transistor.