INFORMATION PROCESSING APPARATUS FOR ENTERTAINMENT SYSTEM UTILIZING DMA-CONTROLLED HIGH-SPEED TRANSFER AND PROCESSING OF ROUTINE DATA

Routine processing for routine data, non-routine processing for routine data and general non-routine processing are to be processed efficiently. To this end, a main CPU 20 has a CPU core 21, having a parallel computational mechanism, a command cache 22 and a data cache 23, as ordinary cache units, and a scratch-pad memory SPR 24 which is an internal high-speed memory capable of performing direct memory accessing (DMA) suited for routine processing. A floating decimal point vector processor (VPE) 30 has an internal high-speed memory (VU-MEM) capable of DMA processing and is tightly connected to the main CPU to form a co-processor. The VPE 40 has a high-speed internal memory 40 (VU-MEM) capable of DMA processing. The DMA controller (DMAC) 14 controls DMA transfer between the main memory 50 and the SPR 24, between the main memory 50 and the (VU-MEM) 34 and between the (VU-MEM) 44 and the SPR 24.