REDUCED TRANSISTORS DATA SWITCH PORT WHEREIN EACH OF A PLURALITY OF TRANSMISSION GATES IS COUPLED TO BOTH FIRST AND SECOND CONTROL SIGNALS FOR SELECTIVELY ENABLING

A high density, high speed, and low power circuit scheme is presented for vector switching port applications for advanced IC design. Embodiments exhibit superior area-delay-power properties. The technique benefits a wide range of product applications ranging from high speed high bandwidth router to low power portable computing hardware. 5.0 TBPS peak traffic can be supported for an on-chip vector port.