METHOD AND APPARATUS FOR INCREASING SIGNAL TO SNEAK RATIO IN POLARIZABLE CROSS-POINT MATRIX MEMORY ARRAYS

A state of a memory element in a memory device is accessed by conditioning a number of wordlines and an addressed one of a number of bitlines in the memory device. This causes an addressed one of the memory elements in the device to release a signal charge and an unaddressed one to release a sneak charge into the addressed bitline. This charge release causes the current in the addressed bitline to increase. This current is integrated, and integration is halted when a signal to sneak ratio of the addressed bitline is maximized. The integration yields a total bitline charge value that may be used to obtain a more accurate measurement of the released signal charge.