MEMORY ADDRESS INTERLEAVING AND OFFSET BITS FOR CELL INTERLEAVING OF MEMORY

Patent №

US 6,480,943

Granted

2002-11-12

Filed 2000

Owner

HEWLETT-PACKARD COMPANY

Lab

AI components

1

hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

09563018

A method provides for interleaved access of a contiguous logical address space formed by a plurality of memories having respective overlapping address spaces. The memories are organized into memory segments, memory segments of equal size from different memories arranged or organized into interleave groups. An initial largest interleave group is selected and a corresponding first interleave entry is generated in a table. The interleave entry maps a corresponding initial logical address space into each of the memory segments corresponding to the first interleave group. A total memory size included thus far in the table is calculated and successive next larger groups that are integer divisors of the total memory, i.e., the partial sums formed by groups selected thus far. These steps are repeated until all of the contiguous logical address space has been mapped onto the memories. A mask may be used to extract portions from a logical address to index into a table mapping the logical address space onto the memories. Another portion of the logical address includes a memory offset.

AI classification

AI hardware0.67
Natural language0.00
Speech0.00
Vision0.00
Machine learning0.00
Evolutionary computation0.00
Planning0.00
Knowledge representation0.00

Ownership

HEWLETT-PACKARD COMPANY

assignment · 111470448

Assignors

DOUGLAS, ROBERT, DICKEY, KENT

On an employer assignment, the assignors are typically the inventors.

© 2026 NYSGPT2525 LLC