METHOD AND APPARATUS FOR PERFORMING SPECULATIVE MEMORY FILLS INTO A MICROPROCESSOR

Patent №

US 6,493,802

Granted

2002-12-10

Filed 1998

Owner

DIGITAL EQUIPMENT CORPORATION

+3 more

Lab

—

AI components

hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

09099396

View graph

According to the present invention a cache within a multiprocessor system is speculatively filled. To speculatively fill a designated cache, the present invention first determines an address which identifies information located in a main memory. The address may also identify one or more other versions of the information located in one or more caches. The process of filling the designated cache with the information is started by locating the information in the main memory and locating other versions of the information identified by the address in the caches. The validity of the information located in the main memory is determined after locating the other versions of the information. The process of filling the designated cache with the information located in the main memory is initiated before determining the validity of the information located in main memory. Thus, the memory reference is speculative.

AI hardwareG06F 12/0815G06F 12/0806G06F 12/0859G06F 12/0862G06F 2212/507

Google Patents

AI classification

AI hardware0.59

Knowledge representation0.00

Natural language0.00

Evolutionary computation0.00

Machine learning0.00

Vision0.00

Planning0.00

Speech0.00

Ownership

DIGITAL EQUIPMENT CORPORATION

assignment · 92560001

COMPAQ INFORMATION TECHNOLOGIES GROUP, L.P.

assignment · 125520813

COMPAQ COMPUTER CORPORATION

merger · 188060727

HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

namechg · 188160834

Assignors

RAZDAN, RAHUL, KELLER, JAMES B., KESSLER, RICHARD E.

On an employer assignment, the assignors are typically the inventors.

From the same owner

TECHNIQUE FOR PROCESSING DATA IN A NETWORKUS 9,122,682 · 2015 METHOD FOR IDENTIFYING RELATED PAGES IN A HYPERLINKED DATABASEUS 7,630,973 · 2009 METHOD AND APPARATUS FOR COMPOSITING COLORS OF IMAGES USING PIXEL FRAGMENTS WITH Z AND Z GRADIENT PARAMETERSUS 7,064,771 · 2006 REDUCTION OF ADD-PIPE LOGIC BY OPERAND OFFSET SHIFTUS 7,043,516 · 2006 APPARATUS AND METHOD FOR FILTERING DOWNLOADED NETWORK SITESUS 6,883,020 · 2005 METHODS AND APPARATUS FOR GENERATING EFFECTIVE TEST CODE FOR OUT OF ORDER SUPERSCALAR MICROPROCESSORSUS 6,813,702 · 2004 METHOD AND APPARATUS FOR QUERY-SPECIFIC BOOKMARKING AND DATA COLLECTIONUS 6,810,395 · 2004 METHOD FOR MANAGING PAGES OF A DESIGNATED MEMORY OBJECT ACCORDING TO SELECTED MEMORY MAGEMENT POLICIESUS 6,804,766 · 2004

Cites (12)

METHOD AND APPARTUS FOR DEVELOPING MULTIPROCESSOR CACHE CONTROL PROTOCOLS USING ATOMIC PROBE COMMANDS AND SYSTEM DATA CONTROL RESPONSE COMMANDSUS 6,314,496 · 2001 DISTRIBUTED DATA DEPENDENCY STALL MECHANISMUS 6,085,294 · 2000 SHARING INSTRUCTION PRECODE INFORMATION IN A MULTIPROCESSOR SYSTEMUS 5,951,671 · 1999 APPARATUS FOR SPECULATIVELY STORING AND RESTORING DATA TO A CACHE MEMORYUS 5,838,943 · 1998 METHOD FOR PROVIDING AND OPERATING UPGRADEABLE CACHE CIRCUITRYUS 5,829,036 · 1998 CACHE CONTROL FOR USE IN A MULTIPROCESSOR TO PREVENT DATA FROM PING - PONGING BETWEEN CACHESUS 5,713,004 · 1998 DIRECTORY-BASED COHERENCE PROTOCOL ALLOWING EFFICIENT DROPPING OF CLEAN-EXCLUSIVE DATAUS 5,680,576 · 1997 SCALABLE CACHE ATTRIBUTES FOR AN INPUT/OUTPUT BUSUS 5,651,137 · 1997 PACKET SWITCHED CACHE COHERENT MULTIPROCESSOR SYSTEMUS 5,634,068 · 1997 COMPUTER SYSTEM AND METHOD FOR MAINTAINING MEMORY CONSISTENCY IN A PIPELINED, NON-BLOCKING CACHING BUS REQUEST QUEUEUS 5,623,628 · 1997 A SYSTEM AND METHOD OF IMPLEMENTING READ RESOURCES TO MAINTAIN CACHE COHERENCY IN A MULTIPROCESSOR ENVIRONMENT PERMITTING SPLIT TRANSACTIONSUS 5,504,874 · 1996 Patent US 5,956,753US 5,956,753

Cited by (7)

MULTI-PROCESSOR SYSTEM RECEIVING INPUT FROM A PRE-FETCH BUFFERUS 8,281,079 · 2012 SYSTEM CONTROLLER, SPECULATIVE FETCHING METHOD, AND INFORMATION PROCESSING APPARATUSUS 7,516,278 · 2009 SYSTEMS AND METHODS FOR EMPLOYING SPECULATIVE FILLSUS 7,409,500 · 2008 REGISTER FILE SYSTEMS AND METHODS FOR EMPLOYING SPECULATIVE FILLSUS 7,409,503 · 2008 MULTI-PROCESSOR SYSTEMS AND METHODS FOR BACKUP FOR NON-COHERENT SPECULATIVE FILLS

Related research

Off-chip prefetching based on Hidden Markov Model for non-volatile memory architecturesSemantic Scholar A Machine Learning Methodology for Cache Memory Design Based on Dynamic InstructionsSemantic Scholar Mitigating the Memory Bottleneck with Machine Learning-Driven and Data-Aware Microarchitectural TechniquesarXiv LCM: LLM-focused Hybrid SPM-cache Architecture with Cache Management for Multi-Core AI AcceleratorsSemantic Scholar Effective Context-Sensitive Memory Dependence PredictionOpenAlex

Full text

Google Patents