A METHOD AND APPARATUS FOR EXTRACTING BRIDGES FROM AN INTEGRATED CIRCUIT LAYOUT

A bridge fault extractor. A computer-implemented method for performing fault extraction from an integrated circuit layout includes determining maximum critical areas from the layout for a maximum defect size of a set of defect sizes to be analyzed wherein each maximum critical area corresponds to a net-name pair. The maximum critical areas are then locally merged by net-name pair to determine an area of a union of maximum critical areas for each net-name pair.Critical areas for defect sizes smaller than the maximum defect size are determined from the maximum critical areas and locally merged by net-name pair to determine an area of a union of critical areas for each net-name pair for each smaller defect size.