SINGLE CYCLE LINEAR ADDDRESS CALCULATION FOR RELATIVE BRANCH ADDRESSING

A method and circuit for linear space target address generation for a relative branch is described. A selection signal is generated to be used in generating a linear space target address. The generation of the linear space target address includes generating multiple corrected target addresses and selecting the linear space target address from the multiple corrected target addresses using the selection signal. The process of generating multiple corrected target addresses includes generating first, second, and third corrected target addresses. The first corrected target address is generated using an address and a displacement. The second corrected target address is generated using the address, displacement, and a second adder correction value. The third corrected target address is generated using the address, displacement, and a third adder correction value. A multiplexer outputs the first, second, or third corrected target address using the selection signal. The selection signal is generated in selection logic using a segment wrap indication and a displacement sign, where the segment wrap indication is generated based on a displacement least significant bits, a segment base, and a least significant address.