SYSTEM FOR SYNCHRONIZING USE OF CRITICAL SECTIONS BY MULTIPLE PROCESSORS USING THE CORRESPONDING FLAG BITS IN THE COMMUNICATION REGISTERS AND ACCESS CONTROL REGISTER

A hardware arrangement for implementing synchronization control between multiple processors is disclosed. The hardware arrangement is provided with a plurality of communication registers which are arranged so as to store synchronization control data applied from the processors. A flag bit register generates a plurality of flag bits which are respectively assigned to a plurality of critical sections. Each of the flag bits indicates whether or not the corresponding critical section is available. In order to assure the mutual exclusion control, a flag bit access control register is provided which generates a plurality of control bits that are respectively assigned to the plurality of flag bits. The control bit is used to prevent two processors from using an identical critical section. A controller is provided so as to adequately control the above-mentioned registers.