METHOD AND SYSTEM FOR TIMING AND AREA DRIVEN BINARY AND/OR MATCHING

A method and system are disclosed for finding the best match from a target library of simple logic cells for a complex logic circuit conception. The inventive method is flexible and can be adapted to several cost functions or criteria. The inventive method finds the best children nodes for a match of simple gates (AND, OR, NAND, NOR). The method allows one to improve the overall area of the final design while respecting the time constrains. It also allows one to smartly speed up the tiler process as this process does not have to investigate exhaustive lists of possible children. Two preferred embodiments are disclosed. One such embodiment is designed to improve slack time and the other is designed to minimize required area.