RACE CONDITION DETECTION AND EXPRESSION

A method and apparatus for improved race detection and expression is disclosed. The race detection method and apparatus disclosed herein detects races statically by analyzing the circuits, which are usually written in a hardware description language (HDL), such as VHDL or Verilog. Compared with known simulation approaches, the inventive method and apparatus has at least the following advantages: no test vectors are required; all potential races can be detected; and in simulator approaches, if the right test vectors are not provided, then the races cannot be found (the invention avoids this last constraint).