NEW LEAKAGE-TOLERANT KEEPER WITH DUAL OUTPUT GENERATION CAPABILITY FOR DEEP SUB-MICRON WIDE DOMINO GATES
Patent №
US 6,549,040
Granted
2003-04-15
Filed 2000
Owner
INTEL CORPORATION, A CORP. OF DELAWARE
Lab
—
AI components
1
hardware
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
09608683
A circuit including a clock signal input to receive a clock signal, at least one data signal input to receive at least one data signal, and a multiple input conditional inverter to receive the clock signal and the data signal, and to generate a dynamic output. The circuit also includes a conditional keeper circuit to charge a dynamic output node when the clock is evaluating and the dynamic output is high.
AI classification
Ownership
INTEL CORPORATION, A CORP. OF DELAWARE
assignment · 111230086
Assignors
ALVANDPOUR, ATILA, SOUMYANATH, KRISHNAMURTHY, KRISHNAMURTHY, RAM K.
On an employer assignment, the assignors are typically the inventors.