STATIC TIMING ANALYSIS WITH SIMULATIONS ON CRITICAL PATH NETLISTS GENERATED BY STATIS TIMING ANALYSIS TOOLS
Patent №
US 6,553,549
Granted
2003-04-22
Filed 2000
Owner
CYPRESS SEMICONDUCTOR CORPORATION
Lab
—
AI components
2
ml · hardware
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
09501246
A circuit comprising a plurality of gates and a plurality of control circuits. The plurality of gates may each have an output connected to an input of a next gate of the plurality of gates. The plurality of control circuits may be connected to a second input of one or more gates of the plurality of gates. The plurality of control circuits may simulate switching.
AI classification
AI hardware1.00
Machine learning1.00
Evolutionary computation0.00
Speech0.00
Vision0.00
Planning0.00
Natural language0.00
Knowledge representation0.00
Ownership
CYPRESS SEMICONDUCTOR CORPORATION
assignment · 105600633
Assignors
GOWNI, SHIVA P., MEHROTRA, RAKESH
On an employer assignment, the assignors are typically the inventors.
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