MULTI PROCESSOR SYSTEM AND FIFO CIRCUIT

A multi processor system includes a first processor having a data input terminal and a data output terminal, which first processor is programmed so as to decide destinations to which data items successively input from an input terminal thereto should be delivered and deliver the input data items to the decided destinations, and a plurality of second processors, each of which has a data input terminal and a data output terminal and is programmed so to execute a predetermined process on data items delivered from the first processor. A FIFO circuit includes a memory portion, a write pointer assigned to a first master; and a plurality of read pointers each of which is assigned to one of a plurality of second masters.