DETECTION OF OVERWRITE MODIFICATION BY PRECEDING INSTRUCTION POSSIBILITY OF FETCHED INSTRUCTION CODE USING FETCHED INSTRUCTIONS COUNTER AND STORE TARGET ADRESS

The present invention aims at improving the performance of the process of an information processing apparatus which includes an instruction fetch port, and can detect the possibility for the overwrite of an instruction fetched from the instruction fetch port by correctly detecting the length of an instruction sequence already stored in an instruction buffer for storing an instruction to be fetched before the execution of instructions, and an instruction to be determined in the instructions being or already executed, and by correctly detecting the possibility for the overwrite of the contents of an instruction fetched from one instruction port. The information processing apparatus comprises: an instruction fetch counter unit for counting the length of an instruction sequence containing all instructions which are fetched before the last fetched instruction. The instructions and the last fetched instruction have sequential addresses; and an instruction overwrite possibility determination unit for using an address of an instruction at a specified position in all instruction sequences, a storage target address at which an execution result of a completed store instruction is stored, and an output value of the instruction fetch counter unit, and detecting a possibility for the overwrite of an instruction wherein at least a part of the range of the storage target address overlaps the address of an instruction in all instruction sequences, and at least a part of the instruction sequences is overwritten.