MULTI-THREADED PROCESSING SYSTEM AND METHOD FOR SCHEDULING THE EXECUTION OF THREADS BASED ON DATA RECEIVED FROM A CACHE MEMORY

Patent №

US 6,578,065

Granted

2003-06-10

Filed 1999

Owner

HEWLETT-PACKARD COMPANY

Lab

AI components

1

hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

09405441

A system and method for controlling the scheduling of threads in a multi-thread processor system. The multi-thread processor system has a multi-thread processor, a main memory, a cache memory, and a thread scheduler. Information is sent from the cache memory to the thread scheduler for determining which thread the processor is going to execute. The thread scheduler calculates or maintains a figure of merit for each thread executing on the processor. The figure of merit determines which thread to switch to when the current or previous thread has a long latency. The figure of merit define the execution environment as measured by the performance of the cache memory. The figure of merit can be the owner of a particular thread, the number of data lines accessed by a particular thread which resides in the cache, the number of times a particular thread has hit in the cache over a specified time interval, the thread that installed the data or the thread that was used most recently.

AI hardwareG06F 9/4881G06F 9/3851

AI classification

AI hardware1.00
Machine learning0.00
Knowledge representation0.00
Natural language0.00
Speech0.00
Planning0.00
Evolutionary computation0.00
Vision0.00

Ownership

HEWLETT-PACKARD COMPANY

assignment · 102740587

Assignors

AGLIETTI, ROBERT, ROKICKI, TOMAS G., GUPTA, RAJIV

On an employer assignment, the assignors are typically the inventors.

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