SCALABLE, RE-CONFIGURABLE CROSSBAR SWITCH ARCHITECTURE FOR MULTI-PROCESSOR SYSTEM INTERCONNECTION NETWORKS

The present invention provides a new crossbar switch which is implemented by a plurality of parallel chips. Each chip is completely programmable to couple to every node in the system, e.g., from one node to about one thousand nodes (corresponding to present-day technology limits of about one thousand I/O pins) although conventional systems typically support no more than 32 nodes. The crossbar switch can be implemented to support only one node, then one chip can be used to route all 64 bits in parallel for 64 bit microprocessors.