PROGRAMMABLE PHASE ADJUSTMENT

In a phase matching circuit for generating a system clock signal for an incoming data signal from a locally existing clock signal, a delay signal is calculated from the detected phase position of the data signal in that a memory addressed with the detected phase position outputs an allocated delay signal. In a specific embodiment, the memory is supplied with an address that is compensated by the most recently identified delay. In a further development, a control comprising the memory shares circuits for a number of data signals. The phase matching, which automatically recognizes a jitter compatibility more suitable for the clocking than the jitter compatibility employed at the moment, can be completely integrated and avoids circuit areas that are operated with a higher bit repetition rate than that of the clock signal.