TOOL AND METHOD FOR IMPROVING THE QUALITY OF BOARD DESIGN AND MODELING

The present invention provides a design tool and method which creates a VHSIC Hardware Description Language (VHDL) board model that can be used by digital engineers to verify their ASIC and FPGA designs. (VHSIC is an acronym for Very High Speed Integrated Circuits.) The board model is used as part of the test bench that tests the functionality of the board. Any models of the component parts can be instantiated in the board model using a “configuration” statement in the VHDL. Any inconsistencies between the board requirements and the ASIC and FPGA specifications can be identified.