METHOD AND SYSTEM FOR REDUCING TAKEN BRANCH PENALTY

Patent №

US 6,735,689

Granted

2004-05-11

Filed 2000

Owner

SANDCRAFT INCORPORATED

Lab

AI components

2

planning · hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

09562061

Penalty for taking branch in pipelined processor is reduced by pre-calculating target of conditional branch before branch is encountered, thereby effectively converting branches to jumps. During program execution, pipeline penalty is reduced effectively to that of unconditional jump. Offset bits are replaced in a conditional branch with index bits based on addition of offset bits and a program counter value. Scheme reduces need for cycle to calculate target of taken branch. Scheme may be applied during cache fill or dead cycle when taken branch is read from pipelined cache.

PlanningAI hardwareG06F 9/30058G06F 9/3017G06F 9/322

AI classification

AI hardware1.00
Planning0.92
Natural language0.05
Machine learning0.01
Knowledge representation0.00
Speech0.00
Evolutionary computation0.00
Vision0.00

Ownership

SANDCRAFT INCORPORATED

assignment · 110220281

Assignors

THOMSON, THOMAS W.S., CHOQUETTE, JACK

On an employer assignment, the assignors are typically the inventors.

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