SYSTEM AND METHOD FOR EVALUATING FUNCTIONAL COVERAGE LINKED TO A VERIFICATION TEST PLAN

A system and method for automatic verification of a test plan for a semiconductor device. The device is specified by a hardware description language (HDL) model or a formal description language model derived from the HDL model. A test plan tool and database are provided to capture test item definitions and identifications and a monitor generator is provided to generate monitors for detecting functional coverage during verification. An evaluator is provided to compare verification-events with test-plan items, to determine test item completeness and to update the test plan database.