SYSTEM AND METHOD FOR REDUCING COMPUTATIONAL OVERHEAD IN A SEQUENCED FUNCTIONAL VERIFICATION SYSTEM

Patent №

US 6,745,375

Granted

2004-06-01

Filed 1999

Owner

CIRRUS LOGIC, INC.

Lab

AI components

1

hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

09252174

The computational load of using a sequencer system and the memory allocation requirements demanded for sequencer operation are reduced in operation with functional models that do not require the services of a sequencer. The computational overhead introduced by the sequencer is reduced, and memory resources for a sequencer are diminished. Functional models that do not require sequencing are created with the same framework as functional models that do require sequencing, while eliminating the sequencer's computational overhead for functional models that do not require sequencing, and allowing functional models that to not require sequencing to be created without allocating the memory required to support the sequencer. Further, both sequenced and un-sequenced functional models coexist in the same sequenced verification framework, permitting the un-sequenced functional models to avoid the computational and memory allocation overhead otherwise incurred by the sequencer.

AI classification

AI hardware0.97
Machine learning0.09
Evolutionary computation0.02
Knowledge representation0.01
Vision0.00
Natural language0.00
Speech0.00
Planning0.00

Ownership

CIRRUS LOGIC, INC.

assignment · 97890412

Assignors

CARTER, HAMILTON B.

On an employer assignment, the assignors are typically the inventors.

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