Patent №
US 6,747,657
Granted
2004-06-08
Filed 2001
Owner
INTEL CORPORATION
Lab
—
AI components
1
hardware
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
10038814
A depth write disable apparatus and method for controlling evictions, such as depth values, from a depth cache to a corresponding depth buffer in a zone rendering system. When the depth write disable circuitry is enabled, evictions from the depth cache (as which typically occur during the rendering of the next zone) to the depth buffer are prevented. In particular, once the depth buffer is initialized (i.e. cleared) to a constant value at the beginning of a scene, the depth buffer does not need to be read. The depth cache handles intermediate depth reads and writes within each zone. Since the memory resident depth buffer is not required after a scene is rendered, it never needs to be written. The final depth values for a zone can thus be discarded (i.e., rather than written to the depth buffer) after each zone is rendering.
AI classification
Ownership
INTEL CORPORATION
assignment · 127860235
Assignors
DOYLE, PETER L., SREENIVAS, ADITYA
On an employer assignment, the assignors are typically the inventors.