Patent №
US 6,757,019
Granted
2004-06-29
Filed 2000
Owner
BOARD OF TRUSTEES OF THE LELAND STANFORD JUNIOR UNIVERSITY, THE
AI components
1
vision
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
09523584
The present invention implements a parallel processing architecture in which a plurality of parallel processors concurrently operate upon a different block, preferably a column, of image data. Implemented on a single monolithic integrated circuit chip, this single chip solution has characteristics that provide the throughput necessary to perform computationally complex operations, such as color correction, RGB to YUV conversion and DCT operations in either still or video applications, and motion estimation in digital video processing applications. Particular uses of the invention in systems processing image data according to an MPEG2 image compression technique and according to a digital video (DV) image compression technique are disclosed.
AI classification
Ownership
BOARD OF TRUSTEES OF THE LELAND STANFORD JUNIOR UNIVERSITY, THE
assignment · 109320384
Assignors
HSIEH, JEFF Y.F., MENG, TERESA H.Y.
On an employer assignment, the assignors are typically the inventors.