DIGITAL PROCESSING SYSTEM

A digital processing system P, configured as a regular tree with n+1 levels S0, S1, S2 . . . Sn and degree k, provided in the form of a circuit Pn on the level Sn and forms the root node of the tree, an underlying level Sn−q, q=1,2, . . . n−1, in the circuit P provided nested in the Kq−1 circuits Pn−q+1 on the overlying level Sn−q+1, each circuit Pn−q+1 on this level including k circuits Pn−q. A q=n defined zeroth level in the circuit Pn includes from Kn−1+1 to Kn circuits P0 which form kernel processors in the processing device P and on the level S0 and constitute the leaf nodes of the tree, the kernel processor P0 being provided nested in each of the circuits p1 on the level S1. Each of the circuits P1, P2, . . . Pn, includes a logic unit E which generally is connected with circuits P0, P1, . . . Pn−1. Each of the circuits P0, P1, . . . Pn has additionally identical interfaces I, such that IP0−IP1− . . . IPn.