CACHE WITH SELECTIVE WRITE ALLOCATION

A digital system and method of operation is provided in which several processors (590n) are connected to a shared cache memory resource (500). A translation lookaside buffer (TLB) (310n) is connected to receive a request virtual address from each respective processor. A set of address regions (pages) is defined within an address space of a back-up memory associated with the cache and write allocation in the cache is defined on a page basis. Each TLB has a set of entries that correspond to pages of address space and each entry provides a write allocate attribute (550) for the associated page of address space. During operation of the system, software programs are executed and memory transactions are performed. A write allocate attribute signal (550) is provided with each write transaction request. In this manner, the attribute signal is responsive to the value of the write allocation attribute bit assigned to an address region that includes the address of the write transaction request. Write allocation in the cache memory is performed generally in accordance with the write allocate attribute signal. However, write allocation policy circuitry (560) is also provided and operates to refine the operation of the write allocation. Thus, the cache memory is responsive to the write policy circuitry such that write allocation is performed in a selective manner in accordance to the attribute signal for a first write policy state and write allocation is always performed in accordance to the attribute signal for a second write policy state.