BYTECODE INSTRUCTION PROCESSOR WITH SWITCH INSTRUCTION HANDLING LOGIC

A circuit arrangement and method facilitate the execution of switch instructions such as Java lookupswitch and tableswitch instructions in hardware through emulation of such instructions using a plurality of conditional branch instructions from the same instruction set as the switch instructions, and which are capable of being directly implemented in hardware. The conditional branch instructions are typically generated by switch instruction handling logic and passed to execution logic capable of natively executing the conditional branch instructions. By emulating a complex switch instruction in switch instruction handling logic using a plurality of conditional branch instructions from the same instruction set, often the amount of custom circuitry needed to fully support a complex switch instruction is substantially reduced from what would be required to natively support the switch instruction in the execution logic of a hardware processor. Moreover, compared to software emulation, which typically requires passing control to a software interpreter, the overhead associated with emulating a switch instruction in the instruction fetch logic using multiple conditional branch instructions capable of being natively executed by execution logic offers substantial gains in performance.