SPLIT CONTROL FOR IP READ AND WRITE CACHE MISSES

An apparatus for and method of queuing memory access requests resulting from level two cache memory misses. The requests are preferably queued separately by processor. To provide the most recent data to the system, write (i.e., input) requests are optimally given preference over read (i.e., output) requests for input/output processors. However, instruction processor program instruction fetches (i.e., read-only requests) are preferably given priority over operand transfers (i.e., read/write requests) to reduce instruction processor latency.