METHOD AND APPARATUS FOR EFFICIENTLY GENERATING, STORING, AND CONSUMING ARITHMETIC FLAGS BETWEEN PRODUCING AND CONSUMING MACROINSTRUCTIONS WHEN EMULATING WITH MICROINSTRUCTIONS

An apparatus and method for efficiently generating arithmetic flags in a computer system. The system includes an eflags register to stored partially computed flags computed by an arithmetic logic unit. The stored partial flags are computed in one cycle. The stored flags are decoded by one of two consuming instructions, PRODF or TBIT, in a second cycle.