Patent №
US 6,825,848
Granted
2004-11-30
Filed 1999
Owner
S3 INCORPORATED
Lab
—
AI components
1
hardware
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
09399280
A synchronized two-level cache including a Level 1 cache and a Level 2 cache is implemented in a graphics processing system. The Level 2 cache is further partitioned into a number of slots which are dynamically allocated to texture maps as needed. The reference counter of each of the cache lines in each cache level is tracked so that a cache line is not overwritten with new data prior to transferring old data out to the recipient device. The age status of each cache line is tracked so that the oldest cache line is overwritten first. The use of synchronized two-level cache system conserves system memory bandwidth and reduces memory latency, thereby improving the graphics processing system's performance.
AI classification
Ownership
S3 INCORPORATED
assignment · 102600076
Assignors
FU, CHIH-HONG, LING, I-CHUNG, HSU, HUAI-SHIH
On an employer assignment, the assignors are typically the inventors.